Modern scaled complementary metal-oxide semiconductor (CMOS) processes are typically optimized for digital circuits. Process advancements such as lower voltage power supplies and shorter gate lengths result in low power, high-speed digital circuits, but can also result in higher power, low performance analog circuits. Lower output resistance, reduced power supply voltage, increased threshold variation and gate leakage present design challenges for analog and mixed signal systems.
The design of high-gain operational amplifiers (hereinafter op-amps) is one example of a design challenge resulting from the continued scaling of CMOS processes. High gain op-amps are critical components of many analog and mixed-signal circuits, and are especially important in switched-capacitor implementations of analog circuits including integrators, filters and other applications including analog-to-digital converters. As gate length decreases, the intrinsic gain per unit current of a device also decreases. Although a smaller gate length increases the transconductance gm, the reduction in the output resistance r0 dominates. Moreover, it is not practical to maintain an acceptable intrinsic gain per unit current by using longer devices in a scaled implementation, especially when increased frequency capability is required. In addition, the output resistance of modern scaled devices is not linearly proportional to gate length; increasing the gate length does not significantly increase the output resistance of the device.
Scaled processes generally utilize lower voltages to prevent gate oxide damage or device breakdown during operation. To achieve satisfactory gain in an amplifier designed in a scaled process, it is often necessary to utilize a cascode topology; however, a cascode topology using a reduced supply voltage generally results in a substantially reduced voltage swing. Modern low-voltage scaled processes result in inherently less gain and voltage swing than older processes, consequently widely used analog design styles such as switched-capacitor networks need to be modified to compensate for these effects. Switched-capacitor circuits demand high performance from op-amps included in the circuits. In a highly scaled CMOS process it is generally difficult to achieve the required op-amp performance.